Generally, semiconductor memory devices are divided into volatile memories and nonvolatile memories. The volatile memories, including chiefly random access memories (RAM) such as dynamic random access memories (DRAM) and static random access memories (SRAM), retain their memory data when the power is turned on, but lose the stored data when the power is turned off. In contrast, the nonvolatile memories, including chiefly read only memories (ROM), retain their memory data even after the power is turned off.
The nonvolatile memories may be subdivided into ROM, programmable ROM (PROM), erasable PROM (EPROM), and electrically erasable PROM (EEPROM).
From the view point of process technology, the nonvolatile memories may be divided into a floating gate family and a metal insulator semiconductor (MIS) family comprising a multi-layer of two or more dielectrics. The memory devices of the floating gate family use potential wells to achieve memory characteristics. For instance, EPROM tunnel oxide (ETOX) structures are widely applied to flash EEPROM. On the other hand, the memory devices of the MIS family perform memory functions by using traps positioned on a dielectric bulk, the interface between dielectrics, and the interface between the dielectric and the semiconductor. At present, the MONOS (metal oxide nitride oxide semiconductor)/SONOS (semiconductor oxide nitride oxide semiconductor) structure is chiefly being employed for flash EEPROM.
Jang, U.S. Pat. No. 6,587,396, describes a horizontal surrounding gate (HSG) flash memory cell. In the Jang Patent, the HSG flash memory cell is located on a trench of an isolation region, and a channel region thereof composed of a semiconductor film is sequentially encompassed by a tunneling oxide layer, a floating gate, and a control gate. The floating gate and the control gate are also formed on the trench below the channel region.
Lin et al., U.S. Pat. No. 6,583,466, describes a vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions. The Lin et al. Patent includes forming FET cells in rows and columns with the rows orthogonally arranged relative to the columns, forming FOX regions between the rows, forming a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions formed in the sidewalls, forming doped drain regions near the surface of the substrate, forming doped source regions in the base of the device below the trenches, forming a tunnel oxide layer over the substrate including the trenches, and sequentially forming floating gates, an interelectrode dielectric layer, control gate electrodes, and spacers.
Wu, U.S. Pat. No. 6,084,265, describes a high density, shallow trench, contactless nonvolatile memory. The Wu Patent includes forming a plurality of field oxides on a semiconductor substrate, forming buried bit lines in the semiconductor substrate and beneath the field oxides, forming trenched floating gates between the field oxides over the buried bit lines in the semiconductor substrate, forming tunnel dielectrics between the trenched floating gates and the semiconductor substrate, forming an interpoly dielectric over the field oxides and the trenched floating gates, and forming control gates on the interpoly dielectric.
In conventional flash memory devices, impurities in a source/drain region may be diffused into a channel area. Such diffusion shortens the channel length, thereby causing a short channel effect and deteriorating the device characteristics. In addition, the low capacitance due to small surface areas of the floating gate and the control gate results in a low coupling ratio. Therefore, it is difficult to effectively inject or remove charges in the floating gate. As used herein, the coupling ratio is a ratio of a voltage applied to the floating gate to a voltage applied to the control gate. Due to these problems, conventional flash memory devices may not smoothly perform program and erase functions.